Robust Memory Circuits for VDDmin , Speed and Power Improvement

Supply-voltage (VDD) scaling techniques are often employed in low power System-on-Chip (SoC) design; however, adverse impacts such as voltage-dependent timing skews and small sensing headroom have become increasingly significant on memory circuits. In this dissertation, functional failures induced by voltage-dependent timing skews and small sensing headroom in memory circuits are investigated. Techniques to overcome voltage-dependent timing skews and reduce sensing headroom requirement are proposed. Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed performance of embedded memory. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of memory circuit. A dual-mode self-timed (DMST) technique is developed to eliminate the timing-skew-induced failures and speed degradation across various process, voltage and temperature (PVT) conditions. Comparing to the conventional sense-tracking-only replica column schemes, DMST technique achieves high scalability and timing skews reduction for various bitline (BL) lengths. Experimental results demonstrated that the DMST technique can operate continuously over a wide range of supply-voltage, from